1. Field of the Invention
The present invention generally relates to a processor-based device that supports sharing of a data bus by volatile memory and non-volatile memory.
2. Description of the Related Art
Typically, processor-based systems provide multiple types of memory. One relatively fast memory type is dynamic random access memory (DRAM). A processor typically executes the majority of its programs in DRAM because of DRAM""s speed. One drawback of DRAM is that it is volatile or, in other words, DRAM does not retain its contents once power to the processor-based system is switched off.
Alternatively, read-only memory (ROM) is typically slower than DRAM, but does not lose its contents when the power is switched off. ROM often stores code necessary to xe2x80x9cbootxe2x80x9d the processor-based system and then loads the code to DRAM for execution. To preserve DRAM space, in some processor-based systems, code is executed out of ROM.
The wide disparity of speed between the DRAM and ROM can potentially present significant timing concerns for processor-based systems. Those concerns have been addressed by placing the different types of memory on different address and data buses. Another basic reason for providing DRAM and ROM on separate buses has been to allow for simultaneous DRAM and ROM transactions.
Briefly, a processor-based device, such as a microcontroller, provides a data bus that is shared by both non-volatile memory and volatile memory. The processor-based device also provides specialized signals to facilitate the data bus sharing. A non-volatile memory controller of the processor-based device provides a non-volatile memory busy signal and a non-volatile memory request signal to a volatile memory controller of the processor-based device. The non-volatile memory busy signal indicates to the volatile memory controller when the non-volatile memory controller controls the data bus. The non-volatile memory request signal indicates to the volatile memory controller when the non-volatile memory controller needs to use the data bus. The volatile memory controller provides a volatile memory busy signal to the non-volatile memory controller which informs the non-volatile memory controller when the data bus is controlled by the volatile memory controller.
By providing the non-volatile memory busy signal, the non-volatile memory request signal and the volatile memory busy signal, a processor-based device can effectively support a data bus shared by a non-volatile memory and a volatile memory. In the disclosed embodiment, the non-volatile memory is a read-only (ROM) or flash device, the volatile memory is a synchronous dynamic random access memory (SDRAM) device and the shared data bus is the DRAM data bus.
The volatile-memory controller can include a write buffer and a volatile-memory arbiter having a write buffer state and a processor bus master state. Transactions to volatile memory or non-volatile memory use a processor bus in addition to the shared data bus. When the volatile-memory arbiter is in the write buffer state, the write buffer can initiate a write buffer cycle using the shared data bus. When the volatile-memory arbiter is in the write buffer state and a non-volatile memory request signal is asserted, the volatile-memory arbiter transitions to the processor bus master state. In the processor bus master state, the write buffer cannot initiate a write buffer cycle. In this way, collisions between write buffer accesses to the volatile memory and accesses to the non-volatile memory are avoided.
Further, the non-volatile controller provides a buffer enable signal to enable a 5V non-volatile memory device to share the data bus with a 3.3V volatile memory device that is not 5V tolerant. By providing the buffer enable signal, the non-volatile memory controller can activate an isolation buffer between the non-volatile memory controller and the non-volatile memory device. The buffer between the 5V non-volatile memory device and the non-volatile memory device is activated during access of the 5V non-volatile memory device to prevent damage to the 3.3V volatile memory device which can share the same data bus.